I will briefly explain the development of secure processor architectures in industry and academia – in particular, the impact of the Aegis and Ascend architectures in 2003 and 2012. This teaches us that minimizing the Trusted Computing Base in any architecture or system is a HW/SW/Crypto co-design in which we combine HW isolation, efficient crypto, and small trusted SW kernels. This motivates current ongoing research trajectories which will also be described in general terms.
If time permits (but this seems unlikely), I will explain Oblivious RAM (ORAM), explain Path ORAM and its application to secure processor architectures, and we will revisit its definitional framework showing a Bogus ORAM which satisfies ORAM's orginal definition but defeats the whole purpose for introducing ORAM. (May be one/some of you like to collaborate and extend this into a paper.)